Integrated circuits (ICs) and other electronic devices often include arrangements of interconnected field effect transistors (FETs), also called metal-oxide-semiconductor field effect transistors (MOSFETs), or simply MOS transistors or devices. A typical MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain electrodes. A control voltage applied to the gate electrode controls the flow of current through a controllable conductive channel between the source and drain electrodes.
Power transistor devices are designed to be tolerant of the high currents and voltages that are present in power applications such as motion control, air bag deployment, and automotive fuel injector drivers. One type of power MOS transistor is a laterally diffused metal-oxide-semiconductor (LDMOS) transistor. In an LDMOS device, a drift space is provided between the channel region and the drain region.
LDMOS devices may be designed to operate in a high-side configuration in which all of the device terminals are level shifted with respect to the substrate potential. Devices configured for high-side operation have been applied in power switchers in DC-to-DC converters, which have respective LDMOS devices for the high side and low side. High-side capable devices may be designed to prevent a direct punch-through path from a body region of the LDMOS device to an underlying, heavily doped substrate.
LDMOS devices are often used in applications, such as automotive applications, involving operational voltages greater than 45 Volts. Breakdown resulting from applying such high voltages to the drain is often prevented through a reduced surface field (RESURF) structure of the LDMOS device design. The RESURF structure is designed to deplete the drift space of the LDMOS device in both vertical and lateral directions, thereby reducing the electric field in the PN junctions surrounding the drift region and thus raising the breakdown voltage (BVDSS) of the device. Some LDMOS devices have a “double RESURF” structure, in which the drift space contains both n-type and p-type regions. The double nature of the structure refers to the depletion of the two regions and the reduction of the electric field in the related junction areas. Double RESURF structures typically apply the drain voltage to isolation regions in order to deplete the both the n-type and p-type regions. However, biasing the isolation regions at the drain voltage increases the field stress between the source of the LDMOS device and a buried isolation layer. Breakdown may instead occur between the source and the buried isolation layer, thereby limiting the breakdown voltage. Efforts to address such source-based breakdown using a lightly doped buried isolation layer have increased substrate injection and compromised electrostatic discharge (ESD) performance.